1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device. In particular, the present invention relates to a semiconductor technology including transistors having a gate electrode and a gate insulating film.
2. Description of the Related Art
High integration and high speed of a transistor have been realized by means of microfabrication of the transistor on the basis of the scaling law. In general, though polysilicon/SiON and SiO2 are used as a gate stack material of a gate electrode/gate insulating film of a transistor, it has become difficult to make the gate insulating film thin due to an electrical reason. Then, the “high-k/metal gate technology” which is a combination of a high dielectric constant (high-k) gate insulating film and a metal gate electrode attracts attention.
In the case where a metal gate electrode is applied for bulk CMOS (complementary MOS), in order to make it possible to control a threshold value by implanting impurities into channels, metal materials having a different work function from each other are used in an n-type MOS transistor (nMOS) and a p-type MOS transistor (pMOS). Such a gate structure is also called a “dual metal gate structure”. Specifically, in the case of nMOS, a metal material having a work function in the vicinity of a conduction band end of silicon is used, and in the case of pMOS, a metal material having a work function in the vicinity of a valence electron band end is used.
However, in the case where the foregoing “dual metal gate structure” is formed in a usual gate forming process, there is included the following fault. That is, when after forming a metal gate electrode, a high-temperature heat treatment such as annealing is carried out for the purpose of achieving activation, the effective work function of a stack gate composed of a high dielectric constant gate insulting film and a metal gate electrode changes. For that reason, it is difficult to obtain a work function in the vicinity of a desired band end.
Then, there is reported a process in which a dummy gate section is first formed, and after removing this dummy gate section, a gate electrode is formed therein (this process will be hereinafter referred to as “gate-last process”) (see Non-Patent Document 1: Shinpei Yamaguchi, et al., “High Performance Dual Metal Gate with High Mobility and Low Threshold Voltage Applicable to Bulk CMOS Technology” in 2006 Symposium on VLSI Tehcnology Digest of Technical Papers, IEEE, 2006, page 192). In the gate-last process, integration of a dual metal is realized, and very good device characteristics can be obtained. In particular, in the case of the gate-last process, after fabricating a metal material for the purpose of controlling the work function, a device can be formed in a low-temperature process. For that reason, it becomes possible to control an effective work function of the foregoing stack gate in the vicinity of a band end.